RE: [arm-gnu] Using 2006q3-26 with Cortex-M3 (Windows platform)

["Joseph Yiu" <Joseph.Yiu@xxxxxxx>]

Hi all,

I just noticed that the armv7m-crt0.o supplied in the installation
is actually compiled as ARM code, not thumb code.
I guess that's why the linker decide to put zero in the LSB of reset vector.
(It is not good because Cortex-M3 only support thumb/ thumb-2).

Joseph

-----Original Message-----
From: Joseph Yiu [mailto:Joseph.Yiu@xxxxxxx]
Sent: Mon 06/11/2006 12:44
To: arm-gnu@xxxxxxxxxxxxxxxx
Subject: [arm-gnu] Using 2006q3-26 with Cortex-M3 (Windows platform)
 
Hi all,

I am trying to use arm-none-eabi-gcc version 2006q3-26 for
Cortex-M3 code development and found a problem that cause
the core to enter hardfault right after start.

I have a simple program with main, _nmi_isr, _fault_isr.
The following command line is used to compile the program
arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb example6.c -L lib  -T lm3s8xx-rom.ld -o example6.o

Then I disassemble the output using
arm-none-eabi-objdump -t -h -S example6.out > example6.list 

From the disassembled list I found that
00000000 <__DYNAMIC>:
   0:	20002000 	andcs	r2, r0, r0
   4:	00000010 	andeq	r0, r0, r0, lsl r0    <= Problem : LSB of vector=0
   8:	00000225 	andeq	r0, r0, r5, lsr #4
   c:	00000235 	andeq	r0, r0, r5, lsr r2

00000010 <_mainCRTStartup>:
  10:	e59f00c0 	ldr	r0, [pc, #192]	; d8 <.text+0xd8>
  14:	e59f10c0 	ldr	r1, [pc, #192]	; dc <.text+0xdc>
  18:	e1500001 	cmp	r0, r1
  1c:	0a000005 	beq	38 <_mainCRTStartup+0x28>

Since the LSB of reset vector is 0, this cause the core to enter hard fault
immediately.
I tried using lm3s301-rom.ld and it get the same result.
Have anyone find the same problem?
Thanks for your help.
Joseph

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