5.9. Implementation Details

The Sourcery G++ Debug Sprite uses Background Debug Mode, which is supported by all ColdFire cores. In most cases this is completely non-intrusive to the program being debugged. However, if you are using the Sourcery G++ Debug Sprite to debug an operating system kernel (or program with kernel-like features), some of the debugging operations can interact with the program being debugged.

5.9.1. Software Breakpoints

The Debug Sprite uses HALT instructions to implement software breakpoints and semihosting. On execution of a HALT instruction, the Debug Sprite gains control. If the HALT instruction is one that the Debug Sprite inserted itself, it reports a breakpoint to the host's GDB. Semihosting breakpoints are detected by checking for the bit pattern 0x4e7bf000, which corresponds to an unrealistic movec %sp,0 instruction. The semihosting operation will be performed and the program counter adjusted to skip the ill-formed instruction. For all other HALT instructions GDB will report a SIGTRAP.

If the program being debugged uses HALT instructions in an idle loop, each iteration of the idle loop will cause such a SIGTRAP to be reported by GDB. If you want GDB to ignore these signals, enter the following GDB command:

handle SIGTRAP nostop noprint nopass

As HALT is a privileged instruction, the Debug Sprite sets the UHE bit in the CSR so that user mode programs do not raise a privilege violation exception on HALT execution.

5.9.2. Hardware Watchpoints

A single hardware watchpoint is implemented using ColdFire's TDR, AATR, ABLR & ABHR debug registers (Trigger Definition Register, Address Attribute Trigger Register, Address Bus Low Register and Address Bus High Register respectively). A range of addresses can watch for data read, write or access.

Because of the way ColdFire implements the address range check, it is possible for an access to an address just before the range, but whose final byte is within the watched range to be undetected. For instance watching a single byte at address 4N+3 fails to trigger on 32 bit writes to address 4N or on 16 bit writes to address 4N+2.

5.9.3. Single Stepping

Single stepping uses the ColdFire single step feature. This is performed with the IPI (Ignore Pending Interrupts) bit set in the CSR. Without this bit set, single stepping an instruction when an interrupt is pending stops at the first instruction of the ISR, which is undesirable. Thus single stepping a sequence of instructions does not process any interrupts. During continuous execution, interrupts are not so inhibited, and ISRs are executed, if the remainder of the processor state allows them. GDB commands that perform single stepping are step and stepi. Commands that perform continuous execution are continue, jump and finish. The next and nexti commands perform single stepping, except when a function is called, in which case they perform a sequence of single steps to enter the called function, followed by continuous execution for the bulk of the called function.