/*
 */

/*
 * sbd.h: cpu board definitions for IDT 79R361 eval board
 */


#ifndef MHZ
#define MHZ	33		/* max cpu frequency */
#endif

#define SRAM_BASE		0x00000000	/* SRAM */
#define DRAM_BASE		0x04000000	/* DRAM */
#define EXTDUART_BASE		0x1f510000	/* external duart */
#define SONIC_BASE     		0x1f600000	/* ethernet controller */
#define EXPANSION_BASE		0x1f700000	/* expansion connector */
#define PROM_BASE		0x1fc00000	/* prom */
#define BOOTPROM_BASE		0x1fc00000	/* prom */
#define FLASH_BASE		0x1fc00000	/* flash */
#define FLASH_SIZE		0x00200000

#define LOCAL_MEM	SRAM_BASE
#define LOCAL_MEM_SIZE	(1*1024*1024)		/* SRAM size (1Mb) */

/* well known locations used to svae of SRAM and DRAM */
#if __ASSEMBLER__
#define SRAMSIZE	PA_TO_KVA1(0x100)
#define DRAMSIZE	PA_TO_KVA1(0x104)
#else
#define SRAMSIZE	*(unsigned int *)PA_TO_KVA1(0x100)
#define DRAMSIZE	*(unsigned int *)PA_TO_KVA1(0x104)
#endif

/* hardware interrupts */
#define	INTR_SONIC	2	/* Sonic:	int  0 */
#define	INTR_EXTDUART	3	/* Duart:	int  1 */
#define	INTR_284FIX	4	/* 284fix:	int  2 */
#define INTR_MULTI	7	/* internal:	int  5 */

#define INT_SCC_BAUDCLK		3686400
#define EXT_SCC_BAUDCLK		3686400

#if #endian(little)
#define ioaddrw(base,o)	((base)+(o)*4)
#define ioaddrb(base,o)	ioaddrw(base, o)
#define ioaddrh(base,o)	ioaddrw(base, o)
#endif
#if #endian(big)
#define ioaddrw(base,o)	((base)+(o)*4)
#define ioaddrb(base,o)	(ioaddrw(base, o) + 3)
#define ioaddrh(base,o)	(ioaddrw(base, o) + 2)
#endif

/* External SCC */
#define	ExtSerialCommand0	((volatile char *)ioaddrb(PHYS_TO_K1(EXTERNAL_SCC_BASE), 2))	/* Cntl Reg Chan A */
#define	ExtSerialData0		((volatile char *)ioaddrb(PHYS_TO_K1(EXTERNAL_SCC_BASE), 3))	/* Data Reg Chan A */
#define	ExtSerialCommand1	((volatile char *)ioaddrb(PHYS_TO_K1(EXTERNAL_SCC_BASE), 0))	/* Cntl Reg Chan B */
#define	ExtSerialData1		((volatile char *)ioaddrb(PHYS_TO_K1(EXTERNAL_SCC_BASE), 1))	/* Data Reg Chan B */


/* EEPROM support */
#define XICOR_CLKREG    PioDataReg0
#define XICOR_CLKBIT    Pio0Pin12
#define XICOR_DATAREG   PioDataReg1
#define XICOR_DATABIT   Pio1Pin18
#define XICOR_DATADIR   PioDirReg1
#define XICOR_DIRBIT    Pio1Pin18
#define XICOR_DSHIFT    0

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	\
	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

/* XXX these are complete guesses */
#define RAMCYCLE	60			/* 60ns dram cycle */
#define ROMCYCLE	750			/* ~750ns rom cycle */
#define CACHECYCLE	(1000/MHZ) 		/* pipeline clock */
#define CYCLETIME	CACHECYCLE
#define CACHEMISS	(CYCLETIME * 6)
