/*
 * Copyright (c) 2005 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * mips/fenvinline.h : C99 floating point control - MIPS inline functions
 */


#ifndef __FENV_INLINE
#define __FENV_INLINE extern __inline__
#define __FENV_INLINE_defined
#endif

#if !defined(__SOFT_FLOAT) && !defined(__mips16)
__FENV_INLINE
int fetestexcept (int excepts)
{
    unsigned int fcsr;
    /* return flag bits */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    return fcsr & excepts & FE_ALL_EXCEPT;
}    

__FENV_INLINE
int feclearexcept (int excepts)
{
    unsigned int fcsr;
    /* clear flag and cause bits */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    excepts &= FE_ALL_EXCEPT;
    fcsr &= ~((excepts << __FE_MIPS_CAUSE_SHIFT) | excepts); 
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int fegetexceptflag (fexcept_t *fexc, int excepts)
{
    unsigned int fcsr;
    /* save flag bits only */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    *fexc = fcsr & excepts & FE_ALL_EXCEPT;
    return 0;
}    

__FENV_INLINE
int fesetexceptflag (const fexcept_t *fexc, int excepts)
{
    unsigned int fcsr;
    /* restore flag bits only */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    fcsr ^= (fcsr ^ *fexc) & excepts & FE_ALL_EXCEPT;
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int feraiseexcept (int excepts)
{
    unsigned int fcsr;
    /* set flags *and* cause bits */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    excepts &= FE_ALL_EXCEPT;
    fcsr |= (excepts << __FE_MIPS_CAUSE_SHIFT) | excepts; 
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int fegetround (void)
{
    unsigned int fcsr;
    /* return rounding mode */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    return fcsr & 0x3;
}    

__FENV_INLINE
int fesetround (int rounding)
{
    unsigned int fcsr;
    /* set rounding mode */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    fcsr ^= (fcsr ^ rounding) & 0x3;
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int fegetenv (fenv_t *fenv)
{
    unsigned int fcsr;
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    fenv->__fcsr = fcsr;
    return 0;
}    

__FENV_INLINE
int feholdexcept (fenv_t *fenv)
{
    unsigned int fcsr;
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    fenv->__fcsr = fcsr;
    /* clear all exceptions, flags and enable non-stop mode */
    fcsr &= ~((FE_ALL_EXCEPT << __FE_MIPS_CAUSE_SHIFT) 
	      | (FE_ALL_EXCEPT << __FE_MIPS_ENABLE_SHIFT) 
	      | FE_ALL_EXCEPT);
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int fesetenv (const fenv_t *fenv)
{
    unsigned int fcsr, nfcsr;
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    if (fenv == FE_DFL_ENV)
	/* default mode: non-stop */
	nfcsr = FE_TONEAREST;
#ifdef FE_NOMASK_ENV
    else if (fenv == FE_NOMASK_ENV)
	/* traps enabled */
	nfcsr = (FE_ALL_EXCEPT << __FE_MIPS_ENABLE_SHIFT)
	    | FE_TONEAREST;
#endif
    else 
	nfcsr = fenv->__fcsr;
    fcsr ^= (fcsr ^ nfcsr) & 0x00007fff; /* set flags and rounding modes */
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

__FENV_INLINE
int feupdateenv (const fenv_t *fenv)
{
    unsigned int fcsr, nfcsr;
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    if (fenv == FE_DFL_ENV)
	/* default mode: non-stop */
	nfcsr = FE_TONEAREST;
#ifdef FE_NOMASK_ENV
    else if (fenv == FE_NOMASK_ENV)
	/* traps enabled */
	nfcsr = (FE_ALL_EXCEPT << __FE_MIPS_ENABLE_SHIFT)
	    | FE_TONEAREST;
#endif
    else 
	nfcsr = fenv->__fcsr;
    nfcsr |= (fcsr & FE_ALL_EXCEPT);
    fcsr ^= (fcsr ^ nfcsr) & 0x00007fff; /* set flags and rounding modes */
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (fcsr));
    return 0;
}    

#if !defined(_POSIX_SOURCE) && !defined(_ANSI_SOURCE)
/* GNU extensions */
__FENV_INLINE
int feenableexcept (int excepts)
{
    unsigned int fcsr, nfcsr;
    /* set trap enable bits */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    nfcsr = fcsr | ((excepts & FE_ALL_EXCEPT) << __FE_MIPS_ENABLE_SHIFT);
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (nfcsr));
    /* return old enable bits */
    return (fcsr >> __FE_MIPS_ENABLE_SHIFT) & FE_ALL_EXCEPT;
}    

__FENV_INLINE
int fedisableexcept (int excepts)
{
    unsigned int fcsr, nfcsr;
    /* clear trap enable bits */
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    nfcsr = fcsr & ~((excepts & FE_ALL_EXCEPT) << __FE_MIPS_ENABLE_SHIFT);
    __asm__ __volatile ("ctc1 %0,$31" : : "r" (nfcsr));
    /* return old enable bits */
    return (fcsr >> __FE_MIPS_ENABLE_SHIFT) & FE_ALL_EXCEPT;
}    

__FENV_INLINE
int fegetexcept (void)
{
    unsigned int fcsr;
    __asm__ __volatile ("cfc1 %0,$31" : "=r" (fcsr));
    /* return trap enable bits */
    return (fcsr >> __FE_MIPS_ENABLE_SHIFT) & FE_ALL_EXCEPT;
}    
#endif /* ! _POSIX_SOURCE && ! _ANSI_SOURCE */

#endif /* !defined(__SOFT_FLOAT) && !defined(__mips16) */

#ifdef __FENV_INLINE_defined
#undef __FENV_INLINE
#undef __FENV_INLINE_defined
#endif
