/*
 * Copyright (c) 1998-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * NEC41XX/sbd.h: board-specific definitions for NEC Vr41xx eval board
 */


#ifndef _NEC41XX_SBD_H_
#define _NEC41XX_SBD_H_

#ifndef MHZ
/* fastest possible pipeline clock */
#define MHZ		169
#endif

#include <nec/vr41xxio.h>

/* The Vr41xx Count register runs at MasterOut freq, which is Pclock /
   (4 * CLKDIV), where CLKDIV is determined from the CLKSEL pins. */
#define _SBD_CLK_MULT	1
#define _SBD_CLK_DIV	(_sbd_tclkdiv()*4)

/* board device addresses */
#define DRAM_BASE	0x00000000
#define PCMCIA_MEM_BASE	(SYSBUS_MEM_BASE + 0x0000000)
#define ISA_MEM_BASE	(SYSBUS_MEM_BASE + 0x2000000)
#define PCMCIA_IO_BASE	(SYSBUS_IO_BASE + 0x1000000)
#define ISA_IO_BASE	(SYSBUS_IO_BASE + 0x2000000)
#define FLASH_BASE	0x1f000000
#define  FLASH_SIZE	 0x1000000
#define ROM_BASE	0x1fc00000
#define BOOTPROM_BASE	ROM_BASE

/* The board has three ns16550 uarts - two off-chip and one on */
#define ISA_INT		(ISA_IO_BASE + 0xfee0)
#define ISA_INTMSK	(ISA_IO_BASE + 0xfef0)
#define LEDWR_BASE	(ISA_IO_BASE + 0xffa0)
#define FLSHCNT_BASE	(ISA_IO_BASE + 0xffb0)
#define UART0_BASE	(ISA_IO_BASE + 0xffc0)	/* off-chip uart #0 */
#define DEBDSP_BASE	(ISA_IO_BASE + 0xffd0)
#define UART1_BASE	(ISA_IO_BASE + 0x03f0)	/* off-chip uart #1 */
#define PPT_BASE	(ISA_IO_BASE + 0xfff0)
#define UART2_BASE	(SIU_BASE)		/* on-chip uart #2 */

/* How to access ns16550 registers (offsets) */
#define NSREG(x)	((x)*2)

/* ISA_INT and ISA_MSK bits */
#define ISAINTSLOT2 0x0002
#define ISAINTSLOT3 0x0004

/* Flash memory control */
#define FLSHCNT_FRDY	0x80	/* flash RDY pin */
#define FLSHCNT_VPPEN	0x40	/* flash VPP enable */
#define FLSHCNT_DPSW1	0x20	/* dip switch 1 (0=flash boot, 1=rom boot) */
#define FLSHCNT_DPSW2	0x10	/* dip switch 2 (1=normal, 0=exchanged) */

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	\
	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

#define RAMCYCLE	60			/* 60ns single sram cycle */
#define ROMCYCLE	165			/* 165ns single rom cycle */
#define CACHECYCLE	(1000/MHZ) 		/* pipeline clock */
#define CYCLETIME	CACHECYCLE
#define CACHEMISS	(CYCLETIME * 6)

#ifndef __ASSEMBLER__
extern void	sbdusdelay (unsigned int);
extern long	_sbd_tclkdiv (void);
#endif

#endif /* _NEC41XX_SBD_H_ */
