/*
 * Copyright (c) 1996-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * rs381.h: cpu board definitions for IDT RS381 eval board
 */


#define LOCAL_MEM	0x00000000 	/* DRAM */
#define LOCAL_MEM_SIZE	(16*1024*1024)	/* DRAM size (16Mb) */
#define SRAM0_BASE	0x04000000	/* SRAM 0-wait state */
#define SRAMN_BASE	0x04100000	/* SRAM n-wait state */
#define SRAM_SIZE	0x00040000	/* SRAM size (256Kb) */
#define DPRAM_BASE	0x04400000	/* Dual port SRAM */
#define SONIC_BASE	0x1fb00000	/* pc/at interface */
#define PROM_BASE	0x1fc00000	/* prom */
#define DUART_BASE	0x1fe00000 	/* m68681 duart */
#define ERRADDR_BASE	0x1ff00000 	/* bus error address reg */

/* hardware interrupts */
#define	INTR_V3		2	/* V3 bus ctlr:	sint 0 */
#define	INTR_SONIC	3	/* Sonic:	sint 1 */
#define	INTR_SPARE1	4	/* spare 1:	sint 2 */
#define INTR_SPARE2	5	/* spare 2:	int  3 */
#define INTR_SPARE3	6	/* spare 3:	int  4 */
#define INTR_DUART	7	/* duart:	int  5 */

/* S2681 uart defs */
#define S2681REGSZ	4
