/*
 * Copyright (c) 1998-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * IDT364/sbd.h: board-specific definitions for IDT364 board
 */


#ifndef _IDT364_SBD_H_
#define _IDT364_SBD_H_

#ifndef MHZ
/* fastest possible pipeline clock */
#define MHZ		133
#endif

/* device addresses */
#define SRAM_BASE	0x00000000
#define DRAM_BASE	0x00100000
#define	SONIC_BASE	0x10000000
#define PLX_BASE	0x14000000
#define DUART_BASE	0x18000000
#define LED_BASE	0x18100000
#define  LED(n)	 	 (3 - (n))
#define  LED_CLR	 (4)
#define  LED_CSR	 (5)
#define  LED_BLNK	 (6)
#define  LED_LCSR	 (7)
#define RESET_BASE	0x18100008
#define SERRCLR_BASE	0x18100009
#define ISR_BASE	0x1810000a
#define PCIPROBE_BASE	0x1810000b
#define NVRAM_BASE	0x18200000
#define BOOTPROM_BASE	0x1fc00000
#define FLASH_BASE	0x1fc00000
#define FLASH_SIZE	0x400000

#define Z8530CLOCK	3686400
#define Z8530DELAY	0	/* hardware enforces recovery time */

/* uart register layout offsets; 8-bit bus width */
#define Z8530_CHB	0
#define Z8530_CHA	2
#ifdef __ASSEMBLER__
# define Z8530_CMD	0
# define Z8530_DATA	1
# define Z8530RESET(reg) sb zero,4(reg); lbu zero,4(reg)
#else
# define z8530reg0	unsigned char cmd
# define z8530reg1	unsigned char data
# define Z8530RESET(dp)	do {dp[2].cmd = 0; (void)dp[2].cmd;} while (0)
#endif

/* onboard interrupt status register */
#define ISR_BE		0x01
#define ISR_PCI_INTA	0x02
#define ISR_PLX9060	0x04
#define ISR_PCI_SERR	0x08
#define ISR_LOCAL_SERR	0x01
#define ISR_PEND_MASK	0xe0
#define ISR_PEND_SHIFT	5

/* interrupt numbers (in ISR_PEND, all wired to CPU Intr0 */
#define	INTR_UART	0
#define INTR_SONIC	1
#define	INTR_PCIA	2
#define INTR_PCIB	3
#define INTR_PCIC	4
#define INTR_PCID	5
#define INTR_SERR	6
#define INTR_NONE	7

/* board attributes */
#define _SBD_PANEL

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	\
	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

#define RAMCYCLE	60			/* 60ns single sram cycle */
#define ROMCYCLE	165			/* 165ns single rom cycle */
#define CACHECYCLE	(1000/MHZ) 		/* pipeline clock */
#define CYCLETIME	CACHECYCLE
#define CACHEMISS	(CYCLETIME * 6)

#ifndef __ASSEMBLER__
extern void	sbdusdelay (unsigned int);
#endif

#endif /* _IDT364_SBD_H_ */
