#ident "kit/NEC5074L/sbdfreq.c: Copyright (c) MIPS Technologies, Inc. All rights reserved."

/*
 * Copyright (c) 1999-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* 
 * NEC5074/sbdfreq.c: CPU frequency determination for NEC DDB-Vrc5074 board
 */


#ifdef IN_PMON
#include <pmon.h>
#include <sde-compat.h>
#else
#include <stddef.h>
#include <mips/cpu.h>
#include <mips/prid.h>
#include "kit_impl.h"
#endif

#include "sbd.h"
#include "ds1386.h"
#include "vrc5074.h"

#ifdef IN_PMON
#define _sbd_pipefreq		sbdpipefreq
#define _sbd_cpufreq		sbdcpufreq
#define mips_getcount()		get_count()
#define mips_getconfig()	Config

int cpuspeed = MHZ/2;	/* worst case until it gets configured */
#endif

#define RTC_HZ		20
#define RTC_WD_CSECS	0x05

/*
 * Dynamically determine CPU pipeline clock frequency by running the
 * on-chip timer against the Real Time Clock watchdog timer.
 */

long
_sbd_pipefreq (void)
{
    static long pipefreq = 0;
    volatile struct td_clock *td = PA_TO_KVA1 (RTC_BASE);
    unsigned long start, cnt, timeout;
    int i;

    if (pipefreq > 0)
	return pipefreq;

    if (td->td_month & TDMON_DOSC) {
	td->td_command &= ~TDCMD_TE; mips_wbflush();
	td->td_month &= ~TDMON_DOSC; mips_wbflush();
	td->td_command |= TDCMD_TE; mips_wbflush();
    }

    /* enable watchdog i/u and swithch off pulse mode */
    td->td_command &= ~(TDCMD_WAM | TDCMD_PU);
    td->td_wdsecs = 0;
    mips_wbflush();

    /* run more than once to be sure that we're in the cache */
    for (i = 2, cnt = 0; i != 0; i--) {
	start = cnt;
	td->td_wdcsecs = RTC_WD_CSECS;	/* start watchdog */
	/* wait until we see the watchdog flag */
	timeout = 10000000 / RTC_HZ;
	while ((td->td_command & TDCMD_WAF) == 0)
	    if (--timeout == 0) return 0;
	cnt = mips_getcount ();
    }
    cnt -= start;

    /* work out number of counter ticks per sec */
    pipefreq = cnt * RTC_HZ;

    /* pipeline runs at 2x counter rate */
    pipefreq *= 2;

#ifdef IN_PMON
    {
	if (IS_KVA0 (_sbd_pipefreq))
	    cpuspeed = pipefreq / 1000000 / 2;
	else 
	    cpuspeed = ROMUS (1);
    }
#endif

    return pipefreq;
}


/*
 * Return the CPU bus clock frequency (usually same input clock).
 */

long
_sbd_cpufreq (void)
{
    unsigned int ratio = (mips_getconfig() & CFG_ECMASK) >> CFG_ECSHIFT;
    long freq = _sbd_pipefreq ();

    /* standard r5x00 */
    freq /= (ratio + 2); 
    return freq;
}
