/*
 * Copyright (c) 2000-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * IDT134/sbd.h: board-specific definitions for IDT 79S134 board
 */


#ifndef _IDT364_SBD_H_
#define _IDT364_SBD_H_

#ifndef MHZ
/* fastest possible pipeline clock? */
#define MHZ		150
#endif

#ifndef BUS_MHZ
/* fixed system/bus clock */
#define BUS_MHZ		50
#endif

/* device addresses */
#define SRAM_BASE	0x00000000
#define DRAM_BASE	0x00100000
#define DUART_BASE	0x16000000	/* external UART */
#define RC32124_BASE	0x18000000
#define FLASH_BASE	0x1fc00000
#define FLASH_SIZE	0x200000

#define Z8530CLOCK	3686400
#define Z8530DELAY	0	/* hardware enforces recovery time */

/* uart register layout offsets; 8-bit bus width */
#define Z8530_CHB	0
#define Z8530_CHA	2
#ifdef __ASSEMBLER__
# define Z8530_CMD	0
# define Z8530_DATA	1
# define Z8530RESET(reg) sb zero,4(reg); lbu zero,4(reg)
#else
# define z8530reg0	unsigned char cmd
# define z8530reg1	unsigned char data
# define Z8530RESET(dp)	do {dp[2].cmd = 0; (void)dp[2].cmd;} while (0)
#endif

/* Internal UART */
#define UART0_BASE	(RC32124_BASE + 0x800)
#define UART1_BASE	(RC32124_BASE + 0x820)

/* Internal UART runs off bus clock */
#define NS16550_HZ	BUS_MHZ
#if #endian(big)
#define NSREG(x)	((x)*4+3)
#else
#define NSREG(x)	((x)*4+0)
#endif

#ifdef __ASSEMBLER__
/* disable Rx0 & Rx1, but enable Tx0 & Tx1 */
#define NS16550_RESET(base) \
    lw	v0,PA_TO_KVA1(RC32124_BASE + 0x600); \
    and	v0,~0x00f000f0; \
    or	v0,0x00500050; \
    lw	v0,PA_TO_KVA1(RC32124_BASE + 0x600)
#endif

/* Select internal UART as default console */
#if !defined(IDT134_EXT_UART) && !defined(IDT134_INT_UART)
/*#define IDT134_EXT_UART*/
#define IDT134_INT_UART 1
#endif

/* Default baud rate is 38400 on this board */
#define DEFSPEED	38400
#define DBGSPEED	38400

/* CPU interrupt numbers */
#define	INTR_UART	0
#define	INTR_PCIA	1
#define INTR_PCIB	2
#define INTR_RC32134	3
#define INTR_PCIC	4
#define INTR_PCID	5
#define INTR_TIMER	5

/* board attributes */
/*#define _SBD_PANEL*/

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	\
	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

#define RAMCYCLE	60			/* 60ns single sram cycle */
#define ROMCYCLE	165			/* 165ns single rom cycle */
#define CACHECYCLE	(1000/MHZ) 		/* pipeline clock */
#define CYCLETIME	CACHECYCLE
#define CACHEMISS	(CYCLETIME * 6)

#ifndef __ASSEMBLER__
extern void	sbdusdelay (unsigned int);
#endif

#endif /* _IDT134_SBD_H_ */
