/*
 * Copyright (c) 1996-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* 
 * sbd.h: Cogent 4300 board definition header file
 */


#ifndef _COGENT_SBD_
#define _COGENT_SBD_

#ifndef MHZ
#define MHZ		33			/* 33MHz sysclk */
#endif

#define RAMCYCLE	80			/* 80ns dram */
#define ROMCYCLE	150			/* 150ns rom */
#define CYCLETIME	((1000+MHZ/2)/MHZ)	/* cycle time in ns */
#define CACHECYCLE	40
#define CACHEMISS		(CYCLETIME * 6)

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

#ifndef __ASSEMBLER__
/* XXX should be dynamic */
#define nsdelay(ns)	mips_cycle (CACHENS (ns))
#define usdelay(us)	mips_cycle (CACHEUS (us))
#endif

#define EPROM1_BASE	0x0e000000 	/* EPROM */
#define RTCLOCK_BASE	0x0e800000	/* Mk48T02 NVRAM/RTC */
#define UART_BASE	0x0e900000	/* NS16C552 DUART */
#define NIC_BASE	0x0ea00000	/* Ethernet controller */
#define LCD_BASE	0x0eb00000 	/* Alphanumeric display */
#define DIP_BASE	0x0ec00000 	/* DIP Switch */
#define IDROM1_BASE	0x0f100000 	/* Slot 1 IDROM */
#define IDROM2_BASE	0x0f100000 	/* Slot 2 IDROM */
#define IDROM3_BASE	0x0f100000 	/* Slot 3 IDROM */
#define ENDIAN_BASE	0x0f700000 	/* Set littleendian byte enables */
#define EPROM2_BASE	0x0f800000 	/* EPROM */

#define IP_UART		CR_HINT0	/* UART Interrupt pending  */
#define IP_NET		CR_HINT1	/* Network Interrupt pending  */
#define IP_SLOT1	CR_HINT2	/* Slot 1 Interrupt pending  */
#define IP_SLOT2_3	CR_HINT3	/* Slot 2/3 Interrupt pending  */

/* big-endian cpu with uart on 8-bit bus D7:D0 */
#define UART0_BASE	(UART_BASE+0x40)
#define UART1_BASE	(UART_BASE+0x00)
#define NS16550_HZ	3686400
#ifdef __MIPSEB__
#define NSREG(x)	((x*8)+7)
#endif
#ifdef __MIPSEL__
#define NSREG(x)	((x*8))
#endif

/* board attributes */
#define _SBD_PANEL

#endif /* _COGENT_SBD_ */
