#ident "kit/IDT361/sbdfreq.c: Copyright (c) MIPS Technologies, Inc. All rights reserved."

/*
 * Copyright (c) 1996-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* 
 * IDT361/sbdfreq.c: CPU frequency determination for IDT 79S351 board
 */


#include <stddef.h>
#include <time.h>
#include <errno.h>
#include <mips/cpu.h>
#include "idt/r36100.h"

#include "kit_impl.h"
#include "sbd.h"
#include "sonic.h"

#define SONIC_FREQ	5000000		/* clock is 5 MHz (half ethernet) */
#define	TEST_PERIOD	500		/* 500us test period */


/*
 * Dynamically determine CPU clock frequency by running the R36100
 * on-chip timer against the Sonic timer (a known frequency).
 */
long
_sbd_cpufreq (void)
{
    volatile struct sn_reg *snr = (struct sn_reg *) PA_TO_KVA1 (SONIC_BASE);
    unsigned long sr;
    static long cpufreq = 0;
    unsigned long cnt;
    unsigned long cfg;
    p36100;

    if (cpufreq > 0)
	return cpufreq;

    /* make sure we're running at full speed */
    cfg = mips_bicconfig (CFG_RFMASK);

    /* Wait for sonic timer to reach TEST_PERIOD usecs and
     * and then examine CPU cycle count to determine clock freq. */
    cnt = TEST_PERIOD * (SONIC_FREQ / 1000000);
    snr->s_wt1 = 0; snr->s_wt0 = cnt; mips_wbflush();
    snr->s_isr = ISR_TC; mips_wbflush();
    
    sr = mips_bicsr (SR_IE);
    TimerControlReg0 = TimerControlTC | TimerControlPsel1;
    snr->s_cr = CR_ST; mips_wbflush();
    TimerCountReg0 = 0;
    do {
      cnt = TimerCountReg0;
    } while (!(snr->s_isr & ISR_TC));
    TimerControlReg0 |= TimerControlTimerDis;
    ExpIntPendReg0 = ExpInt0TimerTC0;

    snr->s_cr = CR_STP; mips_wbflush();
    snr->s_isr = ISR_TC; mips_wbflush();
    mips_setsr (sr);

    mips_setconfig (cfg);

    /* work out number of cpu sysclk cycles per usec (round to nearest) */
    cnt = (cnt + TEST_PERIOD / 2) / TEST_PERIOD;

    /* convert to cycles per sec */
    cpufreq = cnt * 1000000;

    return cpufreq;
}


long
_sbd_pipefreq (void)
{
    unsigned long freq = _sbd_cpufreq ();
    unsigned int log2 = (mips_getconfig () & CFG_RFMASK) >> CFG_RFSHIFT;
    return (freq >> log2);
}
