/*
 * Copyright (c) 2004 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * mips/mips4ks.h : MIPS 4KS family coprocessor 0 definitions
 */


#ifndef _MIPS4KS_H_
#define _MIPS4KS_H_

#ifdef __cplusplus
extern "C" {
#endif

/* SmartMIPS compliant */
#include <mips/smartmips.h>

#ifdef __ASSEMBLER__

#define C0_SCTRL	$22,0	/* SecurityCtrl */
#define C0_SSWPRNG	$22,1	/* SecuritySwPRNG */
#define C0_SHWSPRN	$22,2	/* SecurityHwPRNG (w/o) */
#define C0_SSCRAMBL	$22,3	/* SecurityScrambling (w/o) */

#else

/* 
 * 4KS SecurityCtrl register  (CP0 Register 22, Select 0)
 */
#define mips32_getsctrl()	_m32c0_mfc0(22,0)
#define mips32_setsctrl(x)	_m32c0_mtc0(22,0,x)
#define mips32_xchsctrl(x)	_m32c0_mxc0(22,0,x)

/* 
 * 4KS SecuritySwPRNG register  (CP0 Register 22, Select 1)
 */
#define mips32_getsswprng()	_m32c0_mfc0(22,1)
#define mips32_setsswprng(x)	_m32c0_mtc0(22,1,x)

/* 
 * 4KS SecurityHwPRNG register  (CP0 Register 22, Select 2)
 * Note: write-only
 */
#define mips32_setshwprng(x)	_m32c0_mtc0(22,2,x)

/* 
 * 4KS SecurityScramble register  (CP0 Register 22, Select 3)
 * Note: write-only
 */
#define mips32_setsscrmbl(x)	_m32c0_mtc0(22,3,x)

#endif

/* 
 * 4KS SecurityCtrl register  (CP0 Register 22, Select 0)
 */
#define C0_SCTRL_SEL_MASK	0x00ff0000
#define C0_SCTRL_SEL_SHFT	16
#define C0_SCTRL_CL		0x00000100
#define C0_SCTRL_RSI_MASK	0x00000007
#define C0_SCTRL_RSI_SHFT	0

#ifdef __cplusplus
}
#endif
#endif /* _MIPS4KS_H_ */
