/*
 * Copyright (c) 2005 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * mips/fenv.h : C99 floating point control - MIPS specific
 */

#ifndef __MIPS_FENV_H
#ifdef __cplusplus
extern "C" {
#endif
#define __MIPS_FENV_H

/* MIPS Cop 1 FCSR: Sticky Flag bits */
#define FE_INVALID	0x40
#define FE_DIVBYZERO	0x20
#define FE_OVERFLOW	0x10
#define FE_UNDERFLOW	0x08
#define FE_INEXACT	0x04

#define FE_ALL_EXCEPT 	(FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW \
			 | FE_UNDERFLOW | FE_INEXACT)

/* Shift left by 5 to get Trap Enable bits */
#define __FE_MIPS_ENABLE_SHIFT	5

/* Shift left by 10 to get Cause bits */
#define __FE_MIPS_CAUSE_SHIFT	10

/* MIPS Cop 1 FCSR: Rounding mode */
#define FE_TONEAREST	0x0
#define FE_TOWARDZERO	0x1
#define FE_UPWARD	0x2
#define FE_DOWNWARD	0x3

/* Saved exception flags. */
typedef unsigned int fexcept_t;

/* Complete floating point environment: the FCSR register. */
typedef struct {
    unsigned int	__fcsr;
} fenv_t;

/* Default floating point environment: round to nearest, non-stop mode. */
#define FE_DFL_ENV	((fenv_t *)-1)

/* Floating point environment: traps enabled. */
#if !defined(_POSIX_SOURCE) && !defined(_ANSI_SOURCE)
#define FE_NOMASK_ENV	((fenv_t *)-2)
#endif

#ifdef __OPTIMIZE__
#include <mips/fenvinline.h>
#endif /* __OPTIMIZE__ */

#ifdef __cplusplus
}
#endif
#endif /* __MIPS_FENV_H */
