/*
 * Copyright (c) 1999-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * NEC41XX/sbdfrom.h: onboard FROM support for NEC Vr41xx UEB
 */


/*
 * Note: assumes DBUS32=1 and 32-bit flash module is fitted.
 */

/* Only supports Intel/Sharp devices */
#define FROM_FAMILY_INTEL	1

/* Fixed device geometry on this board */
#define FROM_WIDTH		2	/* dev width = word */
#define FROM_NCOLS		2	/* 2 devices in parallel */
#define FROM_GROUP		FROM_NCOLS

/* "Variable" device geometry (fixed in this case) */
#define FROM_SECSIZE(fcp)	0x10000 /* 64K per sector */
#define FROM_DEVSIZE(fcp)	0x200000 /* 2MB per chip */
#define FROM_DEVSIZE_LOG2(fcp)	21	/* log2(devsize) */
/*#define FROM_NBANKS(fcp)*/

/* Define to enable debug messages */
/*#define FROM_DEBUG*/

/* Define if code (in particular flash programming code) 
   will never executed be from the flash rom. */
/*#define FROM_NEVER_SELF_PROGRAM*/

/* Enable/disable WR */
#define fromwrenable(fcp) \
    do { \
	volatile struct vr41xxbcu *bcu = PA_TO_KVA1(BCU_BASE); \
	bcu->bcu_cnt1 |= BCUCNT1_ROMWEN0 | BCUCNT1_ROMWEN2; \
    	(void) bcu->bcu_cnt1; \
    } while (0)

#define fromwrdisable(fcp) \
    do { \
	volatile struct vr41xxbcu *bcu = PA_TO_KVA1(BCU_BASE); \
	bcu->bcu_cnt1 &= ~(BCUCNT1_ROMWEN0 | BCUCNT1_ROMWEN2); \
    	(void) bcu->bcu_cnt1; \
    } while (0)

/* Enable/Disable Vpp */
#define fromvppenable(fcp) \
    do { \
	volatile unsigned char *flshcnt = PA_TO_KVA1(FLSHCNT_BASE); \
        *flshcnt |= FLSHCNT_VPPEN; \
    	(void) *flshcnt; \
    	mips_cycle (CACHEUS (1)); \
    } while (0)

#define fromvppdisable(fcp) \
    do { \
	volatile unsigned char *flshcnt = PA_TO_KVA1(FLSHCNT_BASE); \
        *flshcnt &= ~FLSHCNT_VPPEN; \
    	(void) *flshcnt; \
    } while (0)

/* Return h/w protect status for offset */
/* Check for an offset lying in the EPROM region if EPROM boot has
   been selected on DIP switch 1.  Say that this is a "protected"
   sector. We also assume the 4Mbit flash has been enabled 
   (non-WinCE mode) using DIP switch 3. */
#define fromprotected(fcp, offs) \
    ({ \
	volatile unsigned char *__flshcnt = PA_TO_KVA1(FLSHCNT_BASE); \
        (*__flshcnt & FLSHCNT_DPSW1) \
	    ? (((offs) & 0xf00000) == 0xc00000) \
	    : 0; \
    })

