/*
 * Copyright (c) 1997-2003 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * IDT465/sbd.h: board-specific definitions for IDT465 board
 */


#ifndef _IDT465_SBD_H_
#define _IDT465_SBD_H_

#ifndef MHZ
/* fastest possible pipeline clock (250MHz is this enough) */
#define MHZ		250
#endif

/* device addresses */
#define SRAM_BASE	0x00000000
#ifdef IDT465_32BIT
#define DRAM_BASE	0x00200000
#else
#define DRAM_BASE	0x00400000
#endif
#define DUART_BASE	0x1f300000
#define SCSI_BASE	0x1f400000
#define NVRAM_BASE	0x1f500000
#define	SONIC_BASE	0x1f600000
#define EXPANSION_BASE	0x1f700000
#define LED_BASE	0x1f800000
#define BOOTPROM_BASE	0x1fc00000
#define FLASH_BASE	0x1fc00000
#define FLASH_SIZE	0x00200000

#ifndef _SBD_FLASHWIDTH
/* assume 32-bit wide flash, that's how the board is shipped */
#define _SBD_FLASHWIDTH	32
#endif

#define Z8530CLOCK	3686400		/* baud rate clock */
#define Z8530DELAY	2		/* 2us recovery time */

/* uart register layout offsets; data is on 31:24 */
#define Z8530_CHA	0
#define Z8530_CHB	8
#ifdef __ASSEMBLER__
# if #endian(big)
#  define Z8530_CMD	0
#  define Z8530_DATA	4
# endif
# if #endian(little)
#  define Z8530_CMD	3
#  define Z8530_DATA	7
# endif
#else
# if #endian(big)
#  define z8530reg0	unsigned cmd:8; unsigned :24
#  define z8530reg1	unsigned data:8; unsigned :24
# endif
# if #endian(little)
#  define z8530reg0	unsigned :24; unsigned cmd:8
#  define z8530reg1	unsigned :24; unsigned data:8
# endif
#endif

/* interrupt mapping */
#define	INTR_UART	1
#define	INTR_EXPANSION	2
#define INTR_SONIC	3
#define INTR_SCSI	4

/*
 * rough scaling factors for 2 instruction DELAY loop to get 1ms and 1us delays
 */
#define ASMDELAY(ns,icycle)	\
	(((ns) + (icycle)) / ((icycle) * 2))

#define CACHENS(ns)	ASMDELAY((ns), CACHECYCLE)
#define RAMNS(ns)	ASMDELAY((ns), CACHEMISS+RAMCYCLE)
#define ROMNS(ns)	ASMDELAY((ns), CACHEMISS+ROMCYCLE)
#define CACHEUS(us)	ASMDELAY((us)*1000, CACHECYCLE)
#define RAMUS(us)	ASMDELAY((us)*1000, CACHEMISS+RAMCYCLE)
#define ROMUS(us)	ASMDELAY((us)*1000, CACHEMISS+ROMCYCLE)
#define CACHEMS(ms)	((ms) * ASMDELAY(1000000, CACHECYCLE))
#define RAMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+RAMCYCLE))
#define ROMMS(ms)	((ms) * ASMDELAY(1000000, CACHEMISS+ROMCYCLE))

/* XXX these are complete guesses */
#define RAMCYCLE	60			/* 60ns dram cycle */
#define ROMCYCLE	750			/* ~750ns rom cycle */
#define CACHECYCLE	(1000/MHZ) 		/* pipeline clock */
#define CYCLETIME	CACHECYCLE
#define CACHEMISS	(CYCLETIME * 6)

#endif /* _IDT465_SBD_H_ */
