/*
 * Copyright (c) 1996-2006 MIPS Technologies, Inc.
 * 
 * All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 *      * Redistributions of source code must retain the above copyright
 *        notice, this list of conditions and the following disclaimer.
 *      * Redistributions in binary form must reproduce the above
 *      copyright
 *        notice, this list of conditions and the following disclaimer
 *        in the documentation and/or other materials provided with
 *        the distribution.
 *      * Neither the name of MIPS Technologies Inc. nor the names of its
 *        contributors may be used to endorse or promote products derived
 *        from this software without specific prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * P4000/sbdrtpx.h: RTPX board-specific definitions for P4000 board
 */


/* 
 * Interrupt wiring:
 *  HINT5 - hard counter clock
 *  HINT4 - hard debug/panic interupt
 *  HINT3 - EV_IO3 and EV_SONIC
 *  HINT2 - EV_IO2 and EV_DUART
 *  HINT1 - EV_IO1
 *  HINT0 - EV_IO0
 *  SINT1 - unused reserved
 *  SINT0 - unused reserved
 */


/* At IPL2 all interrupts are disabled */
#define _RTPX_MIPS_IPL2_SR	(SR_IE)

#if 0
/* 
 * IPL1 is used in "scheduler mode", and only debug/panic
 * interrupts are enabled.
 */
#define _RTPX_MIPS_IPL1_SR	(_RTPX_MIPS_IPL2_SR | SR_HINT4)

/*
 * The interupts enabled when in user mode
 * enable at least IPL1_SR
 * enable all interupts.
 */
#define _RTPX_MIPS_IPL0_SR	(_RTPX_MIPS_IPL1_SR | SR_IMASK)
#else
/* 
 * IPL1 is used in "scheduler mode", and only debug/panic
 * interrupts are enabled.
 */
extern unsigned int _sbd_ipl1_sr;
#define _RTPX_MIPS_IPL1_SR	_sbd_ipl1_sr

/*
 * The interupts enabled when in user mode
 * enable at least IPL1_SR
 * enable all interupts.
 */
extern unsigned int _sbd_ipl0_sr;
#define _RTPX_MIPS_IPL0_SR	_sbd_ipl0_sr
#endif

/* exported event numbers for interrupt sources */
#define EV_IO0		1
#define EV_IO1		2
#define EV_IO2		3	/* not made available */
#define EV_IO3		4	/* not made available */
#define EV_SONIC	5
#define EV_DUART	6
#define EV_DEBUG	7
#define EV_ACFAIL	8	/* not implemented */
#define EV_SINT0	9	/* not implemented */
#define EV_SINT1	10	/* not implemented */
#define EV_CLOCK	-1	/* internal */
#define SBD_EVN_MAX	16	/* max doorbell events */

#define SBD_CPU_MAX	1	/* must be 1 for now */

/* round-robin every 1ms */
#define _RTPX_RRFREQ	1000
