CS3 provides standard handlers for interrupts, exceptions and traps, but also allows you to define your own handlers as needed. In this section, we use the term interrupt as a generic term for this entire class of events.
Different processors handle interrupts in various ways, but there are two general approaches:
Some processors fetch an address from an array indexed by the interrupt number, and jump to that address. We call these address vector processors.
Others multiply the interrupt number by some constant factor, add a base address, and jump directly to that address. Here, the interrupt vector consists of blocks of code, so we call these code vector processors.
MIPS processors use the code vector model. The remainder of this section assumes that you have some understanding of the specific requirements for your target; refer to the architecture manuals if necessary.
On MIPS ELF targets, CS3 provides interrupt and
exception handling support using the MIPS SDE library interface,
which is integrated with the exception support provided by the
YAMON boot monitor.
The interfaces are modelled on the POSIX signal handling
mechanism and are declared in the C header file
mips/xcpt.h
.
Interrupt handlers typically require special call/return and register usage conventions that are target-specific and beyond the scope of this document. In many cases, normal C functions cannot be used as interrupt handlers.
As an alternative to writing interrupt handlers in assembly language,
on MIPS targets they may be written in C using the
interrupt
attribute. This tells the compiler to generate appropriate function
entry and exit sequences for an interrupt handler.
There are additional MIPS-specific attributes you can specify
to modify the behavior of the interrupt handler.
Refer to the GCC manual for more details about attribute syntax
and usage.