Previous: Predefined Target Types, Up: Target Descriptions
A target description must contain either no registers or all the target's registers. If the description contains no registers, then gdb will assume a default register layout, selected based on the architecture. If the description contains any registers, the default layout will not be used; the standard registers must be described in the target description, in such a way that gdb can recognize them.
This is accomplished by giving specific names to feature elements which contain standard registers. gdb will look for features with those names and verify that they contain the expected registers; if any known feature is missing required registers, or if any required feature is missing, gdb will reject the target description. You can add additional registers to any of the standard features — gdb will display them just as if they were added to an unrecognized feature.
This section lists the known features and their expected contents. Sample XML documents for these features are included in the gdb source tree, in the directory gdb/features.
Names recognized by gdb should include the name of the company or organization which selected the name, and the overall architecture to which the feature applies; so e.g. the feature containing ARM core registers is named `org.gnu.gdb.arm.core'.
The names of registers are not case sensitive for the purpose of recognizing standard features, but gdb will only display registers using the capitalization used in the description.
The `org.gnu.gdb.arm.core' feature is required for ARM targets. It should contain registers `r0' through `r13', `sp', `lr', `pc', and `cpsr'.
The `org.gnu.gdb.arm.fpa' feature is optional. If present, it should contain registers `f0' through `f7' and `fps'.
The `org.gnu.gdb.xscale.iwmmxt' feature is optional. If present, it should contain at least registers `wR0' through `wR15' and `wCGR0' through `wCGR3'. The `wCID', `wCon', `wCSSF', and `wCASF' registers are optional.
The `org.gnu.gdb.mips.cpu' feature is required for MIPS targets. It should contain registers `r0' through `r31', `lo', `hi', and `pc'. They may be 32-bit or 64-bit depending on the target.
The `org.gnu.gdb.mips.cp0' feature is also required. It should contain at least the `status', `badvaddr', and `cause' registers. They may be 32-bit or 64-bit depending on the target.
The `org.gnu.gdb.mips.fpu' feature is currently required, though it may be optional in a future version of gdb. It should contain registers `f0' through `f31', `fcsr', and `fir'. They may be 32-bit or 64-bit depending on the target.
The `org.gnu.gdb.mips.linux' feature is optional. It should contain a single register, `restart', which is used by the Linux kernel to control restartable syscalls.
The `org.gnu.gdb.power.core' feature is required for PowerPC targets. It should contain registers `r0' through `r31', `pc', `msr', `cr', `lr', `ctr', and `xer'. They may be 32-bit or 64-bit depending on the target.
The `org.gnu.gdb.power.fpu' feature is optional. It should contain registers `f0' through `f31' and `fpscr'.
The `org.gnu.gdb.power.altivec' feature is optional. It should contain registers `vr0' through `vr31', `vscr', and `vrsave'.
The `org.gnu.gdb.power.spe' feature is optional. It should contain registers `ev0h' through `ev31h', `acc', and `spefscr'. SPE targets should provide 32-bit registers in `org.gnu.gdb.power.core' and provide the upper halves in `ev0h' through `ev31h'. gdb will combine these to present registers `ev0' through `ev31' to the user.