CS3 provides standard handlers for interrupts, exceptions and traps, but also allows you to define your own handlers as needed. In this section, we use the term interrupt as a generic term for this entire class of events.
Different processors handle interrupts in various ways, but there are two general approaches:
Some processors fetch an address from an array indexed by the interrupt number, and jump to that address. We call these address vector processors.
Others multiply the interrupt number by some constant factor, add a base address, and jump directly to that address. Here, the interrupt vector consists of blocks of code, so we call these code vector processors.
Power processors use the code vector model. The remainder of this section assumes that you have some understanding of the specific requirements for your target; refer to the architecture manuals if necessary.
On Power EABI targets, CS3 provides basic interrupt handling support that works in conjunction with the U-Boot boot monitor.
The CS3 U-Boot BSPs save registers reserved by U-Boot and restore
them at _exit
, but do not preserve the register
contents during program execution.
For this reason, CS3 disables external interrupts
and installs default interrupt handlers
which print debugging information on the U-Boot console.
On targets with floating-point support, an alignment interrupt handler is installed by default. GCC may generate floating-point loads and stores to unaligned addresses; the alignment handler emulates these operations. If you write your own BSP for a target with floating-point support, you may wish to do the same.
For details of the interrupt handling implementation, see the
file uboot-handlers_c.c
and the assembly
sources for __cs3_reset
on supported boards
that are provided in your Sourcery G++ Lite installation.